Semiconductor device, nonvolatile semiconductor storage apparatus using the device, and manufacuture method of the device

ABSTRACT

A semiconductor device which is operable with a small occupied area, high reliability, and low power consumption, a nonvolatile semiconductor storage apparatus using the device and a manufacture method of the device.  
     A semiconductor device of the present invention comprises a first gate insulating film, floating gate, second gate insulating film, and control gate on a semiconductor substrate, and a source area and a drain area formed in the semiconductor substrate on opposite sides of the floating gate, the floating gate comprises a first floating gate and a second floating gate disposed to cover the first floating gate, and an isolating gate is formed on the second floating gate on the side of the semiconductor substrate, and parallel to the first floating gate via an isolating insulating film.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device, anonvolatile semiconductor storage apparatus using the device and amanufacture method of the device, particularly but not limited to apreferable semiconductor device for use in an electrically erasable andprogrammable read only memory (EEPROM), and the like, a nonvolatilesemiconductor storage apparatus using the device and a manufacturemethod of the device.

[0003] 2. Description of the Related Art

[0004] One type of a conventional nonvolatile semiconductor memory(which is mainly ROM) are various EEPROMs. In such a memory frequentlyperform data writing, erasing, reading, and the like are performedelectrically, and rewritten data is held for a very long time.

[0005] In the EEPROM, a cell structure is of a two-layer gate type inwhich, for example, a floating gate is formed on a transistor channelarea via a first gate insulating film, and a control gate is formed onthe floating gate via a second insulating film. By thinning a part ofthe first gate insulating film to such an extent that a tunnel effectoccurs electron injection into and discharge from the floating gate bythe tunnel effect is used for information writing and erasing.

[0006]FIG. 1 is a plan view showing one example of a memory array of anEEPROM. This EEPROM is disclosed, in Japanese Patent ApplicationLaid-Open No. 147389/1995. FIG. 2 is a sectional view along line A-A ofFIG. 1, and FIG. 3 is an equivalent circuit diagram of the memory arrayof FIG. 1.

[0007] This memory array is referred to as an AND type. The main surfaceof a memory array area in a p-type semiconductor substrate 1 is providedwith a buried lit line BD (BD₁, BD₂, . . . ) consisting of an n⁺-typesemiconductor area and a buried source line BS (BS₁, BS₂, . . . ), andthese buried bit lines BD₁, BD₂, . . . and buried source lines BS₁, BS₂,. . . extend parallel to each other along one direction of the memoryarray and are alternately arranged in the array direction.

[0008] A word line W (W₁, W₂, . . . ) is disposed in a directioncrossing at right angles to the buried bit lines BD and buried sourcelines BS, and a memory cell for storing one bit of information is formedin an area in which the word line W, and a buried bit line BD or aburied source line BS intersect one another.

[0009] A block B₁ is an area between a select gate SG₁ and a commonsource line SL. A block B₁′ is formed similar to the block B₁. Theseblocks are symmetric with respect to the line C in FIG. 1. Selecttransistors include select gates SG₁ and SG₁′ respectively and eachblock is selected according to voltages applied to each select gate.

[0010] A memory cell of this memory is constituted of an floating gatetransistor 8 comprising a first gate insulating film 2; a floating gate3; a second gate insulating film 4; a control gate 5 formed integrallywith the word line W; a source area 6 integrated with the buried sourceline BS formed inside the p-type semiconductor substrate 1 and on bothsides of the floating gate 5; and a drain area 7 integrated with theburied bit line BD.

[0011] An interlayer insulating film 9 is formed on the control gate 5,and a bit line D (D₁, D₂, . . . ) is connected to a buried bit line BD(BD₁, BD₂, . . . ) via a contact hole 10 formed in the interlayerinsulating film 9. Moreover, end portions of the buried source lines BS(BS₁, BS₂, . . . ) are connected to the common source line SL. Thecommon source line SL consists of an n⁺-type semiconductor area on themain surface of the p-type semiconductor substrate 1. Furthermore, inthe main surface of the semiconductor substrate 1, a groove 11 forisolating memory cells connected to the same word line W is formed, andan insulating film 12 is buried in the groove 11.

[0012] When a data is written to the memory cell, and for example, whenthe cell connected to a bit line D₁ is a writing cell, and a cellconnected to a bit line D₂ is a non-writing cell, a voltage of 5 V isapplied to the drain area 7 (the buried bit line BD₁) of the writingcell, the source area 6 (the buried source line BS₁) is grounded (0 V),a high voltage of 10 V is applied to the word line W₂ (the control gate5), and a channel hot electron generated in the drain area 7 (the buriedbit line BD₁) is injected to the floating gate 3. Therefore, the data iswritten to the memory cell formed in an area in which the word line W₂and the bit line D₁ intersect one another.

[0013] Moreover, in order to erase the data written to the writing cell,a negative voltage of −10 V is applied to the word line W₂ (control gate5), the drain area 7 (the buried bit line BD₁) is grounded (0 V), avoltage of 5 V is applied to the source area 6 (the buried source lineBS₁), and an electron is drawn toward the source area 6 (the buriedsource line BS₁) from the floating gate 3 by Fowler-Nordheim (FN)tunneling. Therefore, the data is erased from the memory cell formed inan area in which the word line W₂ and the bit line D₁ intersect oneanother.

[0014] In the aforementioned conventional memory cell, since source anddrain are separated from those of an adjacent cell, incorrect writing tothe adjacent cell can be prevented. However, it is very difficult toestablish both high integration and low power consumption as describedlater.

[0015] In the conventional memory cell, a writing system by channel hotelectron (CHE) injection is used. In this system of passing a current toa channel, and injecting a hot electron generated in the drain area 7(the buried bit line BD₁) to the floating gate 3 by a gate electricfield applied to the control gate 5 (the word line W₂), injectionefficiency is remarkably small, as about 10⁻⁷, and a large current ofseveral hundreds of microamperes to several milliamperes is consumedduring writing to one cell. Therefore, a burden to the charge pumpingcircuit is large, and the number of cells to be written at the same timeis limited, or a chip size is enlarged since capacitors of the chargepumping circuit must be large.

[0016] As a countermeasure, a writing system using FN tunneling in achannel area is proposed.

[0017] This is a system of applying the high voltage to the control gate5 (the word line W₂), generating an electric field of 10 to 11 MeV inthe first gate insulating film 2, and injecting the electron to thefloating gate 3 by FN tunneling. Writing is possible with a smallcurrent of several tens to several hundreds of pA per cell, the burdento the charge pumping circuit is small because of a low powerconsumption, the number of cells to be written at one time can beincreased, and capacitors of the charge pumping circuit can be little,so chip size increase can be depressed.

[0018] When the writing is performed using the channel FN tunneling, ahigh voltage of about 19 V is applied to the control gate 5 (the wordline W₂), and 0 V is applied to the bit line (the buried bit line BD₁)of the writing cell. In this case, since the high voltage is uniformlyapplied to the control gate 5 of the cell connected to one word line, awriting inhibition voltage of about 5 V is applied to the bit line (theburied bit lines BD₂, BD₃, . . . ) of the non-writing cell to inhibit FNtunneling in the non-writing cell.

[0019] In this case, when the drain or the source fails to be separatedfrom the adjacent cell, a bit line potential of 0 V for writing exertsan influence on the adjacent cell (for example, the memory cell formedin an area in which the word line W₂ and the bit line D₂ intersect oneanother), and writing is inadvertently performed. Alternatively, anotherphenomenon disadvantageously occurs in which the writing inhibitionvoltage also exerts an influence on the adjacent cell and the writing isnot performed.

[0020] Therefore, when channel FN tunneling writing for realizing thelow power consumption is used in the conventional memory cell, it isessential to separate the source and drain of the cell front the sourceand drain of the adjacent cell, for example, by the isolating groove 11or the like. However, since the isolation structure itself is large,memory cell size is increased, and it is disadvantageously difficult toraise an integration degree.

[0021] Moreover, in the conventional memory cell, because of thepresence of the isolation structure, in order to raise the integrationdegree, the floating gate 3 and the control gate 5 have to beminiaturized. As a result, a large coupling capacity ratio R_(c) cannotbe secured, and it is disadvantageously difficult to realize a lowvoltage. The coupling capacity ratio R_(c) is shown below, where acapacity of a tunnel film is C1 and a capacity between the floating gateand the control gate is C₂.

R _(c) =C ₂(C ₁ +C ₂)

[0022] The present invention has been developed in consideration of theaforementioned circumstances, and an object thereof is to provide asemiconductor device, a nonvolatile semiconductor storage apparatususing the device and a manufacture method of the device, in which theoccupied area of the semiconductor device can be reduced, operation ispossible with low power consumption, and low voltage can be realized.

SUMMARY OF THE INVENTION

[0023] In an embodiment of the semiconductor device of the presentinvention, with a two-layer structure comprising a first floating gateand the second floating gate disposed to cover the first floating gate,a capacity ratio is enlarged, and a low voltage can be realized.

[0024] Moreover, by forming an isolating gate parallel to the firstfloating gate with all isolating insulating film therebetween, anelement isolation function during application of the high voltage issecured, leak current or the like fails to easily occur, and as aresult, incorrect operation is eliminated and reliability is enhanced.

[0025] There can thus be provided a semiconductor device with a smalloccupied area, low power consumption and high reliability.

[0026] In the semiconductor device of the present invention, by formingat least the portion of the first gate insulating film corresponding tothe first floating gate as the tunnel film, data writing can beperformed by channel Fowler-Nordheim (FN) electron injection, and dataerasing can be performed by channel Fowler-Nordheim (FN) electronextraction.

[0027] Moreover, since a sufficient pressure resistance of theinsulating film can sufficiently be obtained on the source area anddrain area, reliability during application of the high voltage isenhanced.

[0028] In the semiconductor device of the present invention, by settingthe insulating layer between the first floating gate and the isolatinggate to be thicker than the tunnel film, even during the channelFowler-Nordheim (FN) electron injection/extraction, there is nopossibility that the electron passes through the insulating layer by thetunnel effect, and an insulating property between the first floatinggate and the isolating gate is enhanced.

[0029] In the nonvolatile semiconductor storage apparatus of the presentinvention, by disposing the semiconductor device described above in therespective intersections of the plurality of buried bit lines and wordlines, the channel Fowler-Nordheim (FN) electron injection/extractioncan be performed, the low power consumption, parallel writing and highreliability can be secured, and the device is preferable particularlyduring large capacity serial access.

[0030] There can thus be provided the nonvolatile semiconductor storageapparatus with the small occupied area, low power consumption, and highreliability.

[0031] The nonvolatile semiconductor storage apparatus of the presentinvention shares the buried bit line with the adjacent semiconductordevice, and controls the isolating gate by a control means. When theisolating gate is turned off by the control means during data writing, awriting inhibition voltage can be applied for each bit of one word.

[0032] For another nonvolatile semiconductor storage apparatus of thepresent invention, in the nonvolatile semiconductor storage apparatusdescribed above, the buried bit line is separated into an odd-numberedburied bit line and an even-numbered buried bit line, and a desiredisolating gate is selected by the odd-numbered buried bit line or theeven-numbered buried bit line.

[0033] For another nonvolatile semiconductor storage apparatus of thepresent invention, the nonvolatile semiconductor storage apparatusdescribed above further comprises selecting means for dividing theplurality of buried bit lines into a plurality of sub-bit lines toselect the sub-bit lines.

[0034] A manufacture method of a semiconductor device of the presentinvention comprises: an isolating gate forming step of successivelyforming a first gate insulating film, isolating gate film and firstinsulating film on a semiconductor substrate, subsequentlyselecting/removing the isolating gate film and first insulating film,and forming an isolating gate and isolating insulating film; aninsulating film forming step of forming an insulating layer on oppositeside portions of the isolating gate and isolating insulating film; afirst floating gate forming step of forming a first floating gate on oneside portion of the insulating layer; and a second floating gate formingstep of forming a second floating gate to cover the first floating gateand isolating insulating film.

[0035] A silicon oxide film as the first gate insulating film, and asilicon nitride film as the first insulating film are preferable.

[0036] In the manufacture method of the semiconductor device, by using aconventional manufacture apparatus as it is, and only slightly changinga manufacture process, the semiconductor device can easily bemanufactured in which the isolating gate is formed on the secondfloating gate on the side of the semiconductor substrate, and parallelto the first floating gate via the isolating insulating film.

[0037] For another manufacture method of the semiconductor device of thepresent invention, the manufacture method of the semiconductor devicedescribed above further comprises, after the first floating gate formingstep: an interlayer insulating film forming step of forming aninterlayer insulating film on the isolating insulating film, insulatinglayer and first floating gate; and a planarizing step of planarizingrespective top surfaces of the isolating insulating film, insulatinglayer, first floating gate and interlayer insulating film to expose thetop surface of the first floating gate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other objects, advantages and features of thepresent invention will be more apparent from the following descriptiontaken in conjunction with the accompanying drawings, in which:

[0039]FIG. 1 illustrates a plan view showing one example of the memoryarray of a conventional EEPROM.

[0040]FIG. 2 illustrates a sectional view along line A-A of FIG. 1.

[0041]FIG. 3 illustrates an equivalent circuit diagram of the memoryarray of the conventional EEPROM.

[0042]FIG. 4 illustrates a plan view showing a main part of a memoryarray of EEPROM according to one embodiment of the present invention.

[0043]FIG. 5 illustrates an equivalent circuit diagram of the memoryarray of the EEPROM according to one embodiment of the presentinvention.

[0044]FIG. 6 illustrates a sectional view along line B-B of FIG. 4.

[0045]FIG. 7 illustrates an explanatory view of a minimum design area ofa memory cell of the present invention.

[0046]FIG. 8 illustrates an explanatory view of the minimum design areaof a conventional memory cell.

[0047]FIG. 9A illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0048]FIG. 9B illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0049]FIG. 9C illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0050]FIG. 9D illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0051]FIG. 9E illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0052]FIG. 9F illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0053]FIG. 9G illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0054]FIG. 9H illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0055]FIG. 9I illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0056]FIG. 9J illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0057]FIG. 9K illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0058]FIG. 9L illustrates a process diagram showing a manufacture methodof the memory cell of the present invention.

[0059]FIG. 10 illustrates a process diagram showing a manufacture methodafter FIG. 9F of the memory cell of the present invention.

[0060]FIG. 11 illustrates a block diagram showing a semiconductor memoryaccording to one embodiment of the present invention.

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0061] A semiconductor device, nonvolatile semiconductor storageapparatus using the device and manufacture method according to oneembodiment of the present invention will be described with reference tothe drawings. It is understood that the invention is not limited to thisembodiment, which is provided as only one example of an implementationof the invention. For example the invention is not restricted toEEPROMS, is applicable to other memories such as flash memories andmemories in general where the memory cell isolation is a concern

[0062]FIG. 4 is a plan view showing a main part of a memory array of allEEPROM which is an example of a nonvolatile semiconductor storageapparatus that may advantageously use the present invention, FIG. 5 isan equivalent circuit of the memory array of FIG. 4, and FIG. 6 is asectional view along line B-B of FIG. 4.

[0063] Referring to FIGS. 4-6, the main surface of a memory array areaof a p-type silicon substrate (semiconductor substrate) 1 is providedwith a buried bit line B (+₁, +₂, +₃, . . . ) consisting of an n⁺-typesemiconductor area. An isolating gate line IG (IG₁, IG₂, . . . )parallel to the buried bit line B (+₁, +₂, +₃, . . . ) is formed on thesemiconductor substrate 1, a word line W (W₁, W₂, . . . ) is disposed onthe semiconductor substrate 1 in a direction crossing at right angles tothe buried bit line B (+₁, +₂, +₃, . . . ) and isolating gate line IG(IG₁, IG₂, . . . ), and a memory cell for storing one bit of informationis formed in an area in which the word line W intersects a buried bitline B and an isolating gate line IG.

[0064] For example, a memory cell 21 belongs to the second bit line B(B:+₂).

[0065] In the memory cell 21, on the main surface of the p-type siliconsubstrate 1, a first floating gate 23 is formed via a tunnel oxide film(silicon oxide film) 22 (first gate insulating film), and an isolatinggate 25 is formed via an isolating gate oxide film (silicon oxide film)24. An isolating insulating film 26 which may be of a silicon nitridefilm is formed on the isolating gate 25.

[0066] The first floating gate 23 is formed next to the isolating gate25 and separated therefrom by an insulating film 29.

[0067] Side surfaces of the first floating gate 23, isolating gate 25and isolating insulating film 26 are covered with an interlayer oxidefilm (interlayer insulating film) 27. A second floating gate 28 isformed on the first floating gate 23 and on isolating insulating film 26to cover them. It is understood that the invention also includes, forexample, the first floating gate formed integrally with the secondfloating gate as a unitary structure.

[0068] A control gate 5 is formed on the second floating gate 28 via asecond gate insulating film 4.

[0069] A source area 6 and drain area 7 consisting of an n⁺-typesemiconductor integrated with a buried bit line B (+₁, +₂, +₃, . . . )are formed in the p-type semiconductor substrate 1 on respective sidesof the first floating gate 23 and isolating gate 25. This source area 6serves as the drain area of the adjacent memory cell 21′, and the drainarea 7 serves as the source area of the adjacent memory cell (not shown)which belongs to the bit line B (B:+3).

[0070] Moreover, formed between the first floating gate 23 and theisolating gate 25 is the insulating film 29 which may be of siliconoxide thicker than the tunnel oxide film 22.

[0071] The tunnel oxide film 22 may be thick to such an extent that theelectron can pass through by the tunnel effect during channelFowler-Nordheim (FN) electron injection/extraction performed towrite/erase data.

[0072] Moreover, the thickness t of the insulating film 29 is preferablylarger than thickness t_(f) of the tunnel oxide film 22, more preferablytwice as large as the thickness when both films are of silicon oxide.

[0073] Even during the channel Fowler-Nordheim (FN) electroninjection/extraction, there is no possibility that the electron passesthrough the insulating film 29 by the tunnel effect.

[0074] For the memory cell 21, when a minimum design dimension that isfor exposure and etching steps is F as shown in FIG. 7, each length ofthe isolating gate 25 and first floating gate 23 in a direction of wordline W is F. Each first floating gate 23 is able to be made shorterlength, but it is practically made length F because of its reliabilityEach length of the common source area 6 and drain area 7 is F/2 exceptfor the overlapped length for the common source area 6 and the isolatinggate 25 and the overlapped length for the common drain area 7 and thefirst floating gate 23, because the F/2 is a half of the distance Fbetween the isolating gate 25 of the memory cell 21 and the firstfloating gate 23′ of the memory cell 21′. A width of the common sourcearea 6 and drain area 7 in a direction of bit line B is F. A distancefrom a boundary line with the adjacent memory cell is F/2, then aminimum design area per memory cell is 6F².

[0075] On the other hand, for the conventional memory cell, as shown inFIG. 8, each length of the floating gate 3, source area 6 and drain area7 in the direction of the word line W is F, the distance from theboundary line with the adjacent memory cell of an isolation band 30 isF/2, the width in the direction of the bit line B is F, and the distancefrom the boundary line with the adjacent memory cell is F/2, then theminimum design area per memory cell turns to be 8F².

[0076] Therefore, the minimum design area 6F² of the memory cell 21 at amemory cell according to the invention is ¾ of the minimum design area8F² of the conventional memory cell.

[0077] A method of manufacturing the memory cell 21 will next bedescribed with reference to FIGS. 9A to 9L. Other manufacturing methodsmay be used and the invention is not limited to the manufacturing methoddescribed herein.

[0078] First, as shown in FIG. 9A, the surface of the p-type siliconsubstrate 1 is oxidized, and a silicon oxide film 31 with a thickness of10 to 20 nm is formed to constitute the tunnel oxide film 22 andisolating gate oxide film 24.

[0079] Subsequently, on the silicon oxide film 31, a polysilicon film 32with a thickness of 100 to 200 nm is deposited by a low-pressurechemical vapor deposition (LPCVD) method, and P (phosphorous) or othern-type impurities are doped to provide a concentration of about 1×10²⁰cm⁻³.

[0080] Additionally, the doping may be performed while the polysiliconfilm 32 is deposited, or may be performed by a diffusion method or anion injection method.

[0081] Subsequently, on the n-type polysilicon film 32, a siliconnitride film 33 with a thickness of 20 to 30 nm is deposited by theLPCVD method, and the laminated film is patterned to form the isolatinggate 25 and isolating insulating film 26.

[0082] Subsequently, as shown in FIG. 9B, a silicon oxide film 34 with athickness of 10 to 30 nm is deposited by the LPCVD method, and as shownin FIG. 9C, the silicon oxide film 34 is etched back by anisotropicetching to form a side wall 35 consisting of the silicon oxide film onboth sides of the isolating gate 25 and isolating insulating film 26. Inthis case, the silicon oxide film 31 is removed excluding a portionpositioned under the isolating gate 25 and side wall 35.

[0083] Additionally, for the side wall 35, instead of depositing thesilicon oxide film 34, n-type polysilicon as a main component of theisolating gate 25 is subjected to thermal oxidation, the silicon oxidefilm of about 10 nm is formed on both sides of the isolating gate 25,and both sides of silicon nitride as the main component of the isolatinginsulating film 26 may be modified.

[0084] Subsequently, as shown in FIG. 9D, thermal oxidation isperformed, and the tunnel oxide film 22 with a thickness of about 8 to10 nm is formed on an exposed surface of the p-type silicon substrate 1,that is, the exposed surface outside the side wall 35.

[0085] Subsequently, as shown in FIG. 9E, a polysilicon film 36 with athickness of 200 to 300 nm is deposited by the LPCVD method, and P orother n-type impurities are doped to provide a concentration of about1×10¹⁹ to 1×10²⁰ cm⁻³. Additionally, the doping may be performed whilethe polysilicon film 36 is deposited, or may be performed by thediffusion method or the ion injection method.

[0086] Subsequently, as shown in FIG. 9F, the polysilicon film 36 isetched back by the anisotropic etching to form a polysilicon side wall37 outside the side wall 35.

[0087] Subsequently, as shown in FIG. 9G, by removing the polysiliconside wall 37 on a source side using a etching mask 39 showed in FIG. 10,the polysilicon side wall 37 on a drain side is formed into the firstfloating gate 23.

[0088] Additionally, in a memory array to which the memory cell 21 isapplied, the polysilicon side wall 37 is fixed to either one of thesource side and drain side as for all the memory cells.

[0089] Subsequently, as shown in FIG. 9H, the isolating insulating film26, side wall 35 and first floating gate 23 are used as a mask, As(arsenic) or other n-type impurities are doped in an area for formingthe source and drain of the p-type semiconductor substrate 1 to providea concentration of about 1×10²⁰ cm⁻³, and the source area 6 and drainarea 7 consisting of the n⁺-type semiconductor are formed. The sourcearea 6 and drain area 7 are integrated with the buried bit line B (+₁,+₂, +₃, . . . ).

[0090] Subsequently, as shown in FIG. 9I, by the LPCVD method or a highdensity plasma (HDP) CVD method, a silicon oxide film 38 with athickness of 500 nm to 1 μm is deposited to constitute an interlayeroxide film.

[0091] Subsequently, as shown in FIG. 9J, the isolating insulating film26 is used as a stopper in a CMP (chemical-mechanical polishing) methodto polish and planarize the silicon oxide film 38, so that the Lopsurface of the first floating gate 23 is exposed. The planarized siliconoxide film 38 serves as the interlayer oxide film 27.

[0092] In this case, a polishing depth is adjusted in such a manner thatthe thickness of the planarized isolating insulating film 26 is securedin a range of about 10 to 15 nm.

[0093] Subsequently, as shown in FIG. 9K, on the planarized surface, apolysilicon film 41 with a thickness of 50 to 200 nm is deposited by theLPCVD method, and P or other-type impurities are doped to provide aconcentration of about 1×10²⁰ cm⁻³. Additionally, the doping may beperformed while the polysilicon film 41 is deposited, or may beperformed by the diffusion method or the ion injection method.

[0094] The polysilicon film 41 is patterned, and the second floatinggate 28 is formed to cover the first floating gate 23 and isolatinginsulating film 26.

[0095] Subsequently, on the gate, an interpolymer film 42 with an oxidefilm reduced thickness of 10 to 25 nm is deposited by the LPCVD methodto form the second gate insulating film 4. As the interpolymer film 42,for example, a lamination structure is preferable which comprises threelayers of a 4 to 10 nm thick silicon oxide film, 4 to 10 nm thicksilicon nitride film, and 4 to 10 nm thick silicon oxide film.

[0096] Subsequently, as shown in FIG. 9L, on the second gate insulatingfilm 4, by the LPCVD method a 10 to 20 nm thick polysilicon oxide filmand a 10 to 20 nm silicide film are successively grown to form apolycide film 43.

[0097] Subsequently, the polycide film 43 is patterned to form thecontrol gate 5.

[0098] During the patterning, not only the polycide film 43 which is tohe the control gate 5, but also the interpolymer film 42, secondfloating gate 28, and first floating gate 23 are successively etched,and the first floating gate 23 and second floating gate 28 are dividedin a direction along the bit line B (direction perpendicular to a sheetsurface of FIG. 9). In this case, for the isolating gate 25, theisolating insulating film 26 serves as a stopper, and the isolating gate25 is continuously structured in the direction along the bit line B.

[0099] As described above, the memory cell 21 is formed on the p-typesilicon substrate 1.

[0100]FIG. 11 is a block diagram showing a semiconductor memory of thepresent embodiment, and in the drawing, numeral 51 denotes a memoryarray which comprises memory cells 21 arranged in matrix. Numeral 52denotes an X decoder for inputting an address signal into the memoryarray 51 in order to select one word line W (W₁, W₂, . . . ) on writing,reading, and erasing data in the memory cell. Numeral 53 denotes a Ydecoder for inputting an address signal into the memory array 51 inorder to select one buried bit line B (+₁, +₂, +₃, . . . ) on writingand reading data in the memory cell. Numeral 54 denotes a sub Y decoder(selecting means), disposed between the memory array 51 and the Ydecoder 53, for driving one isolating gate line IG to select anodd-numbered bit line or an even-numbered bit line. Numeral 55 denotes asensing amplifier for amplifying data outputted from the memory array51.

[0101] An operation of the semiconductor memory will next be described.

[0102] (1) Writing TABLE 1 Writing Isolating gate Word voltage Drainvoltage Source voltage voltage Non- Select Non-select Non- Non- Selectselect (write) (non-write) Select select Select select Operation 19 0 05 Open Open 0 0 voltage (V)

[0103] After erasing the information of all memory cells connected to aword, writing is performed by a word unit in parallel by channel FNelectron injection.

[0104] For example, when writing is performed on the memory cellbelonging to an n-th bit line (B:+_(n)), all isolating gates are turnedOFF, and a bit line (B:+_(n+1)) corresponding to the drain is selected.Moreover, with writing of data ‘1’ the bit line (B:+_(n+1)) is grounded(0 V is applied), and with writing of data ‘0’ writing inhibitionvoltage of about 5 V is applied to the bit line (B:+_(n+1)). Thereafter,a high voltage of about 19 V is applied to the word line W to performthe writing.

[0105] In this case, since an isolated transistor has the isolating gateOFF, the voltage supplied to the bit line (B:+_(n)) fails to participatein the writing to the memory cell which belongs to the n-th bit line(B:+_(n)). That is called Open state of the source of the memory cellwhich belongs to the n-th hit line (B:+_(n)).

[0106] Additionally, in Table 1, the bit line for writing the data ‘1’is represented as select (write), and the bit line for writing the data‘0’ is represented as non-select (non-write).

[0107] (2) Erasing TABLE 1 Erasing Isolating gate Word voltage Drainvoltage Source voltage voltage Non- Select Non-select Non- Non- Selectselect (write) (non-write) Select select Select select Operation −16 0Open Open Open Open 0 0 voltage (V)

[0108] Erasing is performed by channel FN electron extraction and by aword unit.

[0109] All the isolated transistors have their isolating gates IG turnedOFF, and all the bit lines B is Open. In this case, all the drains ofall the memory cells are Open. Since all the isolated transistor havingtheir isolating gates IG OFF, the voltage supplied to the bit line(B:+_(n)) fails to participate in the erasing to the memory cell whichbelongs to the n-th bit line (B:+_(n)). That is called Open state of thesource of the memory cell which belongs to the n-th bit line (B:+_(n)).After that, the erasing is performed by applying a negative voltage ofabout −16 V to the word line W.

[0110] (3) Reading TABLE 1 Reading Isolating gate Word voltage Drainvoltage Source voltage voltage Non- Select Non-select Non- Non- Selectselect (write) (non-write) Select select Select select Operation 0-5 0 1Open 0 Open 3.3 0 voltage (V)

[0111] For example, in a case in which data is read from the memory cellto which the even-numbered bit line (B:+_(2n)) belongs, an isolatinggate line IG_(2n) is turned ON, an isolating gate line IG_(2n−1) isturned OFF, the bit line (B:+_(2n)) is selected as the source, and a bitline (B:+_(2n+1)) is selected as the drain.

[0112] Subsequently, the bit line (B:+_(2n)) of the memory cell isgrounded (0 V), a voltage of 1 V is applied to the bit line (B:+_(2n+1))a voltage of 3.3 V is applied to the isolating gate line IG_(2n), and avoltage between 0 V and 5 V is applied to the word line W₂ (control gate5).

[0113] Moreover, in a case in which data is read from the memory cell towhich the odd-numbered bit line (B:+_(2n−1)) belongs, the isolating gateline IG_(2n) is turned OFF, the isolating gate line IG_(2n−1) is turnedON, the bit line (B:+_(2n−1)) is selected as the source, and the bitline (B:+_(2n)) is selected as the drain.

[0114] Subsequently, the bit line (B:+_(2n−1)) of the memory cell isgrounded (0 V), a voltage of 1 V is applied to the bit line (B:+_(2n)),a voltage of 3.3 V is applied to the isolating gate line IG_(2n−1), anda voltage between 0 V and 5 V is applied to the word line W₂ (controlgate 5).

[0115] As described above, according to the memory cell 21 of thepresent embodiment, since the isolating gate 25 and isolating insulatingfilm 26 are formed parallel to the first floating gate 23, and thesecond floating gate 28 is formed on the first floating gate 23 andisolating insulating film 26 covers these, a large capacity ratio can besecured by forming the floating gate in the two-layer structure.

[0116] Since the interlayer oxide film 27 formed on the source area 6and drain area 7 is constituted by the silicon oxide film 38, thethickness can sufficiently be increased, the pressure resistance canthus be enhanced, and the high voltage can be applied to the controlgate 5.

[0117] Since the source area 6 of the memory cell 21 is shared with thedrain area of the adjacent memory cell 21, and the drain area 7 isshared with the source area of the adjacent memory cell, by turning OFFthe isolating gate 25 during data writing, the writing inhibitionvoltage can be applied to each bit of one word.

[0118] As described above, by using the memory cell 21 with a small areaof 6F² according to the present invention, a memory such as an EEPROM,flash memory and the like can be realized in which low powerconsumption, parallel writing, and high reliability can be secured andthe channel FN writing/erasing is used.

[0119] One embodiment of the semiconductor device of the presentinvention, nonvolatile semiconductor storage apparatus using the deviceand manufacture method has been described above with reference to thedrawings, but concrete constitution is not limited to the presentembodiment, and design can be changed within the scope of the presentinvention.

[0120] For example, in the present embodiment the memory array may be ofNOR type, but the type is not limited, and another type of memory arraymay also be used.

[0121] Moreover, the number, shape, and the like of the buried bit lineB, isolating gate line IG, and word line W can appropriately be changedin accordance with required properties of the memory array.

[0122] As described above, according to the semiconductor device of thepresent invention, since the floating gate is of the two-layer structurewhich comprises the first floating gate and the second floating gatedisposed to cover the first floating gate, the capacity ratio can beincreased, and low voltage can be realized.

[0123] Moreover, since the isolating gate is formed parallel to thefirst floating gate via the isolating insulating film, the elementisolation function during application of the high voltage can beenhanced, and as a result, the reliability can be enhanced.

[0124] As described above, there can be provided the semiconductordevice with the small occupied area, low power consumption, and highreliability.

[0125] According to the nonvolatile semiconductor storage apparatus ofthe present invention, since the semiconductor device of the presentinvention is disposed on the respective intersections of the buried bitline and word line, the channel FN electron injection/extraction can beperformed, and there can be provided the nonvolatile semiconductorstorage apparatus with the small occupied area, low power consumption,parallel writing, and high reliability.

[0126] According to the manufacture method of the semiconductor deviceof the present invention, by using the conventional manufactureapparatus as it is, and only slightly changing the manufacture process,the semiconductor device can easily be prepared in which the isolatinggate is formed on the second floating gate on the semiconductorsubstrate side and parallel to the first floating gate via the isolatinginsulating film.

[0127] It is apparent that the present invention is not limited to theabove embodiments, but may be modified and changed without departingfrom the scope and spirit of the invention.

What is claimed is:
 1. A semiconductor device comprising: a first gateinsulating film on a semiconductor substrate, an isolating gateelectrode on said first gate insulating film, an isolating insulatingfilm on the top surface of said isolating gate electrode and a sidesurface of said isolating gate electrode, a floating gate on saidisolating insulating film, a second gate insulating film on saidfloating gate; and a control gate on said second gate insulating film;wherein said floating gate comprises a first floating gate portion whichis on said first gate insulating film and is adjacent to said isolatinggate electrode through a part of said isolating insulating film on saidside surface of said isolating gate electrode and a second floating gateportion which is on said first floating gate portion and on a part ofsaid isolating insulating film on said top surface of said isolatinggate electrode.
 2. The semiconductor device as claimed in claim 1wherein said isolating insulating film on said side surface of saidisolating gate electrode is thicker than said first gate insulatingfilm.
 3. The semiconductor device as claimed in claim 1 furthercomprising; a source region and a drain region in said semiconductorsubstrate on opposite sides of said floating gate.
 4. A nonvolatilesemiconductor memory device comprising: a plurality of buried bit linesarranged in a semiconductor substrate, a plurality of word lines on saidsemiconductor substrate arranged to intersect the buried bit lines; anda plurality of said semiconductor devices which arcis disposed atrespective intersections of said buried bit lines and said word lines,each of said semiconductor devices includes: a first gate insulatingfilm on a semiconductor substrate, an isolating gate electrode on saidfirst gate insulating film, an isolating insulating film on the topsurface of said isolating gate electrode and a side surface of saidisolating gate electrode, a floating gate on said isolating insulatingfilm, a second gate insulating film on said floating gate, a controlgate on said second gate insulating film; and a source region and adrain region in said semiconductor substrate on opposite sides of saidfloating gate; wherein said floating gate comprises a first floatinggate portion which is on said first gate insulating film and is adjacentto said isolating gate electrode through a part of said isolatinginsulating film on said side surface of said isolating gate electrodeand a second floating gate portion which is on said first floating gateportion and on a part of said isolating insulating film on said topsurface of said isolating gate electrode.
 5. The nonvolatilesemiconductor memory device as claimed in claim 4 wherein said pluralityof buried bit lines includes said drain regions and said plurality ofword lines include said control gate.
 6. The nonvolatile semiconductormemory device as claimed in claim 5 further comprising; a X decoderwhich selects one of said word lines, a Y decoder which selects one ofsaid buried bit lines; and a sub Y decoder which selects one of saidisolating gates.
 7. The nonvolatile semiconductor memory device asclaimed in claim 6 wherein said X decoder includes means for supplying afirst individual voltage to one of said word lines which a selectedsemiconductor device belongs to, said Y decoder includes means forsupplying a second individual voltage to one of said buried bit lineswhich is adjacent to said selected semiconductor device, said sub Ydecoder includes means for selecting none of said isolating gates at awriting time.
 8. The nonvolatile semiconductor memory device as claimedin claim 6 wherein said X decoder includes means for supplying a firstindividual voltage to one of said word lines which a selectedsemiconductor device belongs to, said Y decoder includes means forsupplying a second individual voltage to none of said buried bit lines,said sub Y decoder includes means for selecting none of said isolatinggates at a erasing time.
 9. The nonvolatile semiconductor memory deviceas claimed in claim 6 wherein said X decoder includes means forsupplying a first individual voltage to one of said word lines which asemiconductor device to read belongs to, said Y decoder includes meansfor supplying a second individual voltage to one of said buried bitlines which said semiconductor device to read belongs to and includesmeans for supplying a third individual voltage to one of said buried bitlines which is adjacent to said semiconductor device to read, said sub Ydecoder includes means for selecting one of said isolating gates whichbelongs to said semiconductor device to read.
 10. A manufacture methodof a semiconductor device comprising: forming an first gate insulatingfilm on a semiconductor substrate, forming an isolating gate electrodeon said first gate insulating film, forming an isolating insulating filmon the top surface of said isolating gate electrode and a side surfaceof said isolating gate electrode, forming a floating gate on saidisolating insulating film, forming a second gate insulating film on saidfloating gate; and forming a control gate on said second gate insulatingfilm; wherein said floating gate comprises a first floating gate portionwhich is on said first gate insulating film and is adjacent to saidisolating gate electrode through a part of said isolating insulatingfilm on said side surface of said isolating gate electrode and a secondfloating gate portion which is on said first floating gate and on a partof said isolating insulating film on said top surface of said isolatinggate electrode.
 11. The manufacture method of the semiconductor deviceas claimed in claim 10 further comprising after forming an isolatinginsulating film: forming a side wall of said isolating gate electrodeand said isolating insulating film as a first floating gate portion; andforming a second floating gate portion on said isolating insulating filmand said side wall.
 12. The manufacture method of the semiconductordevice as claimed in claim 11 , wherein said isolating insulating filmon said side surface of said isolating gate electrode is thicker thansaid first gate insulating film.
 13. The manufacture method of thesemiconductor device as claimed in claim 11 further comprising: removingone of said side wall corresponding to one of said isolating gateelectrode to remain the other of said side wall.
 14. The manufacturemethod of the semiconductor device as claimed in claim 11 furthercomprising after forming a side wall: forming an interlayer insulatingfilm On said isolating insulating film and said side wall; andconducting CMP to said interlayer insulating film to remove saidinterlayer insulating film on said side wall.